Strained Si NMOSFETs for high performance CMOS technology

Author

Rim, K. ; Koester, S. ; Hargrove, M. ; Chu, J. ; Mooney, P.M. ; Ott, J. ; Kanarsky, T. ; Ronsheim, P. ; Ieong, M. ; Grill, A. ; Wong, H.-S.P.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2001

fDate

12-14 June 2001

Firstpage

59

Lastpage

60

Abstract

Performance enhancements in strained Si NMOSFETs were demonstrated at L/sub eff/<70 nm. A 70% increase in electron mobility was observed at vertical fields as high as 1.5 MV/cm for the first time, suggesting a new mobility enhancement mechanism in addition to reduced phonon scattering. Current drive increase by /spl ges/35% was observed at L/sub eff/<70 nm. These results indicate that strain can be used to improve CMOS device performance at sub-100 nm technology nodes.

Keywords

CMOS integrated circuits; MOSFET; electric current; electron mobility; elemental semiconductors; nanotechnology; semiconductor device measurement; silicon; 100 nm; 70 nm; CMOS device performance; CMOS technology; Si-SiGe-SiO/sub 2/; current drive; effective channel length; electron mobility; mobility enhancement mechanism; performance enhancement; reduced phonon scattering; strained Si NMOSFETs; technology nodes; vertical fields; CMOS process; CMOS technology; Capacitive sensors; Germanium silicon alloys; MOSFETs; Particle scattering; Raman scattering; Silicon germanium; Strain control; Tensile strain;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-012-7

Type

conf

DOI

10.1109/VLSIT.2001.934946

Filename

934946