Performance improvement of metal gate CMOS technologies

Metal gate CMOS technologies for high speed applications were investigated using the damascene metal gate process (Yagishita et al., 1999). We demonstrated the performance improvement by no gate depletion effect in the metal gate using actual devices. Ti/W was used as a single work function metal gate material and ultra shallow buried channel profile was formed for threshold voltage control. The self-aligned channel structure effectively reduces source/drain junction capacitance. An extremely good metal/SiO/sub 2/ interface with the CVD-TiN gate stack realizes intrinsic channel mobility. The propagation delay time of a CMOS inverter ring oscillator was 20 ps, and projected next generation performance would be better due to the improved technologies.