DocumentCode :
3262259
Title :
Accumulator based test-per-scan BIST
Author :
Karpodinis, P. ; Kagaris, D. ; Nikolos, D.
Author_Institution :
Comput. Eng. & Informatics Dept., Patras Univ., Greece
fYear :
2004
fDate :
12-14 July 2004
Firstpage :
193
Lastpage :
198
Abstract :
Arithmetic function modules, which are available in many circuits, can be utilized to generate test patterns and compact test responses. Recently, an accumulator behaving in test mode as a non-linear feedback shift register (NLFSR) has been proposed for bit-serial test pattern generation. However, this structure has the disadvantage that the maximum period of the generated bit sequence depends on the suitable selection of a constant additive value (CAV), which is based on an exhaustive trial and error procedure. In this paper, we propose a slightly modified structure and a heuristic for speeding up significantly the searching of a suitable CAV. We also show, experimentally, that the proposed structure, in most cases, compares favorably to LFSRs and the other arithmetic function based bit-serial sequence generators.
Keywords :
automatic test pattern generation; binary sequences; boundary scan testing; built-in self test; digital arithmetic; logic testing; CAV; LFSR; NLFSR; accumulator based BIST; arithmetic BIST; arithmetic function based generators; arithmetic function modules; bit-serial test pattern generation; constant additive value; nonlinear feedback shift register; test-per-scan BIST; Arithmetic; Built-in self-test; Circuit testing; Compaction; Degradation; Feedback; Hardware; Informatics; Shift registers; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Symposium, 2004. IOLTS 2004. Proceedings. 10th IEEE International
Print_ISBN :
0-7695-2180-0
Type :
conf
DOI :
10.1109/OLT.2004.1319687
Filename :
1319687
Link To Document :
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