DocumentCode :
3262339
Title :
On combining fault classification and error propagation analysis in RT-Level dependability evaluation
Author :
Ammari, A. ; Hadjiat, K. ; Leveugle, R.
Author_Institution :
TIMA Lab., Grenoble, France
fYear :
2004
fDate :
12-14 July 2004
Firstpage :
227
Lastpage :
232
Abstract :
Early analysis of the functional impact of faults aims either at classifying the faults according to their main potential effect, or at analyzing more in depth the error propagation paths in the circuit. This paper presents the results of extensive SEU-like fault injections performed on a VHDL model of the 8051 micro-controller. The advantage of combining the two types of analyses and the impact of the workload are discussed.
Keywords :
VLSI; fault simulation; hardware description languages; high level synthesis; microcontrollers; 8051 microcontroller; RT-level dependability evaluation; SEU-like fault injections; VHDL model; critical configurations; data registers; error propagation analysis; fault classification; high level description; CMOS technology; Circuit faults; Circuit simulation; Electrical fault detection; Error analysis; Error correction; Failure analysis; Fault detection; Fault diagnosis; Process design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Symposium, 2004. IOLTS 2004. Proceedings. 10th IEEE International
Print_ISBN :
0-7695-2180-0
Type :
conf
DOI :
10.1109/OLT.2004.1319692
Filename :
1319692
Link To Document :
بازگشت