Title :
Impact of low-standby-power device design on hot carrier reliability
Author :
Murakami, E. ; Umeda, K. ; Yamanaka, T. ; Kimura, S. ; Aono, H. ; Makabe, K. ; Okuyama, K. ; Ohji, Y. ; Yoshida, Y. ; Minami, M. ; Kuroda, K. ; Ikeda, S. ; Kubota, K.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
The hot-carrier (HC) reliability of low-standby-power 0.1 /spl mu/m n-MOSFETs is investigated, and design guidelines for channel and halo profiles are described. The heavy channel-doping needed to obtain high V/sub th/ enhances HC-injection efficiency, and heavy halo-doping dramatically reduces the lifetime when using substrate-bias (V/sub bb/). Shallow-channel and tilted-halo doping is optimal to keep the HC-generation site away from the SiO/sub 2/-Si interface and to minimize the vertical electric field that is responsible for secondary impact ionization.
Keywords :
MOSFET; doping profiles; hot carriers; interface states; semiconductor device models; semiconductor device reliability; semiconductor device testing; HC-generation site; HC-injection efficiency; SiO/sub 2/-Si; SiO/sub 2/-Si interface; channel profile; design guidelines; halo profile; heavy channel-doping; heavy halo-doping; hot carrier reliability; low-standby-power device design; n-MOSFETs; secondary impact ionization; shallow-channel doping; substrate-bias; threshold voltage; tilted-halo doping; vertical electric field minimization; Current measurement; Degradation; Doping; Hot carriers; Impact ionization; Maintenance; Monitoring; Thickness measurement; Tunneling; Very large scale integration;
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
DOI :
10.1109/VLSIT.2001.934978
