DocumentCode
3263085
Title
A 12bit 100MSps pipelined ADC without calibration
Author
Cai, Xiaobo ; Li, Fule ; Li, Weitao ; Zhang, Chun ; Wang, ZhiHua
Author_Institution
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Volume
8
fYear
2010
fDate
16-18 Oct. 2010
Firstpage
3547
Lastpage
3552
Abstract
A 1.8V 12bit 100MS/s pipelined ADC in 0.18um CMOS process is presented. The first stage adopts 3.5-bit structure to relax the capacitor matching requirements. Bootstrapped switch and scaling down technique are used to improve the ADC´s linearity and save power dissipation respectively. With a 2.4 MHz input signal, the ADC achieves 68.9dB SFDR and 9.3 ENOB at 101MS/s. The power consumption is 180mW at 1.8V supply including output drivers. The chip area is 3.51 mm2 including pads.
Keywords
CMOS integrated circuits; analogue-digital conversion; bootstrap circuits; CMOS process; bootstrapped switch; capacitor matching; frequency 2.4 MHz; pipelined analog-digital converters; power 180 mW; power dissipation; scaling down technique; size 0.18 mum; voltage 1.8 V; word length 12 bit; Bonding; Calibration; Capacitors; Clocks; Operational amplifiers; Switches; Wire; behavioral simulation; multi-bit; opamp; pipelined ADC; reference;
fLanguage
English
Publisher
ieee
Conference_Titel
Image and Signal Processing (CISP), 2010 3rd International Congress on
Conference_Location
Yantai
Print_ISBN
978-1-4244-6513-2
Type
conf
DOI
10.1109/CISP.2010.5647134
Filename
5647134
Link To Document