An interface between VHDL and EDIF

The VHSIC hardware description language (VHDL) and the electronic design interchange format (EDIF) are industry standards for describing design data. The author examines the application range of each standard and the way each standard relates to the other. He discusses the motivation for relating VHDL and EDIF, as well as scenarios in which VHDL and EDIF can contribute to different aspects of the design process.<>