Software defined radio implementation of K-best list sphere detector algorithm

In this novel study, a real-valued signal model based on the K-best list sphere detector (LSD) algorithm is implemented to fixed-point digital signal processor (DSP). A 2 times 2 multiple-input multiple-output (MIMO) antenna system with 64-quadrature amplitude modulation (64-QAM) is assumed. Our former studies proved that software sorting does not meet the real-time requirements, and, thus, in the current studies we assume a hardware sorter. The chosen list size K=16 is based on the simulation results carried out in MATLAB environment. We implemented the K-best LSD algorithm with Sandblaster multithreaded processor and achieved the throughput of 17.9 Mbps, when the hardware sorter was assumed beside the digital signal processor. This novel study shows that the general-purpose digital signal processor has potential to achieve high throughput, when hardware accelerated sorter is assumed. In the current study, the latency of the control code and partial Euclidean distance (PED) calculations were decreased, but the latency of memory loads and stores are significant. We will also compare results from x86 processor architecture and application-specific instruction set processor (ASIP) implemented by using transport triggered architecture (TTA), in which the same parameters were used. The TTA has benefits compared to DSPs, especially in data transmission.