Improving memory subsystem performance in network processors with smart packet segmentation

Network processing requirements are climbing at an impressive rate. The introduction of state-of-the-art, high-speed optical links puts additional strain on all electronic components of a network processor. This is particularly true for the memory subsystem, since the traditional performance gap between memory and processor is also present there. A major contribution to improve the performance of the memory subsystem is to define an optimized algorithm for segmenting network packets. The goal is to ensure a minimum number of segments, so as to achieve maximum packet throughput, while maintaining a high level of memory efficiency. In this paper we present two different algorithms, both of which utilize a variable number of segments from different sizes and evaluate them using a variety of stimuli and system configurations in order to determine how different architectural choices impact the performance of the algorithms and the system in general. The results verify that multiple segment size segmentation provides very high storing efficiency with a low number of segments per packet, thus allowing for significantly higher system throughput in comparison with currently used algorithms.