A fast finite field multiplier architecture for high-security cryptographic applications

As an indispensable part of modern consumer electronics, security applications such as smart cards and network securities play an important role. In fact, data security gets ever-increasing attention as people tend to communicate with each other by various electronic devices over networks. In this paper, a new approach on designing a finite field multiplier architecture is proposed. The proposed architecture trades reduction in the number of clock cycles with resources. This architecture features high performance, simple structure, scalability and independence on the choice of the finite field to provide maximum security to applications so that it can be applied to various fields of security-demanding consumer electronic applications