Flexible design of wide-pipeline-based WiMAX QC-LDPC decoder architectures on FPGAs using high-level synthesis

A novel wide-pipeline low-density parity-check (LDPC) decoder approach for the worldwide interoperability for microwave access (WiMAX) standard (802.16e) is proposed for execution on field-programmable gate arrays (FPGAs), using a high-level synthesis tool to reduce the development effort and design validation time that generates a wide-pipeline architecture. Optimised open computing language (OpenCL)-based kernels are developed and the integration of distinct configurations of single instruction multiple data and compute units to increase the level of parallelism are analysed. The decoding throughput surpasses the minimal requirements of 75 Mbit/s, a key figure of merit that ranks the design with other very large-scale integration-based approaches. Furthermore, extra precision is deployed with 8-bit fixed-point arithmetic, delivering superior bit error rate performance and lower error floor regions.