10 GHz PLL using active shunt-peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18 μm CMOS

When designing circuits operating at high frequencies, some design techniques are quite useful. Some recommended techniques include using MCML gate structures, simple structures, inductive loads and symmetric gates. By considering all these elements in the design process, a PLL working at speeds above 10 GHz has been realized in standard 0.18μm CMOS process. In simulations, the PLL locked onto a reference clock with a period of 94 ps in little over 200 ns. This circuit was implemented and sent to TSMC for fabrication.