A comprehensive calibration scheme for a 14-b 50 MSPS pipeline ADC for multi-mode wireless receivers

Nonidealities of the analog circuitry that degrade the performance of pipeline analog to digital converters stem from different sources. Linear, nonlinear and memory errors in switched capacitor amplifier, nonlinearities in internal DAC, and errors in internal ADC all limit the achievable accuracy in a pipeline ADC. Although many calibration techniques have been proposed recently that tackle one or two of these errors, the need for a calibration engine that addresses them all is still remained. Such a comprehensive calibration engine is the key factor to achieve high resolution high speed pipeline converter. This paper proposes a new approach to compensate for higher order nonlinearities and combines that with existing techniques to correct for other types of errors (i.e. linear gain error, memory effect and DAC noise). A 14-bit 50 Msps pipeline ADC equipped with this comprehensive calibration engine is presented.