DocumentCode :
3266762
Title :
Architecture of a configurable Centered Discrete Fractional Fourier Transform processor
Author :
Sinha, Pavel ; Sarkar, Saibal ; Sinha, Amitabha ; Basu, Dhruba
Author_Institution :
Concordia Univ., Montreal
fYear :
2007
fDate :
5-8 Aug. 2007
Firstpage :
329
Lastpage :
332
Abstract :
This paper presents a novel, configurable architecture for real-time computation of the centered discrete fractional Fourier transform (CDFRFT). The proposed architecture exploits the advantages of both spatial and temporal parallelism in computing the N point CDFRFT of N equally spaced fractional domains in between time and frequency, where N is an integer power of 2. A detailed study of the hardware complexity and the implementation details have been achieved through HDL synthesis, timing analysis and resource utilization. Further, to validate the architecture, it has been implemented on a Xilinx FPGA.
Keywords :
Fourier transforms; field programmable gate arrays; hardware description languages; reconfigurable architectures; HDL synthesis; Xilinx FPGA; centered discrete fractional Fourier transform; configurable processor architecture; hardware complexity; integer power; real-time computation; resource utilization; spatial parallelism; temporal parallelism; timing analysis; Computer architecture; Cost function; Field programmable gate arrays; Fourier transforms; High performance computing; Parallel processing; Resource management; Signal processing algorithms; Time frequency analysis; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
Conference_Location :
Montreal, Que.
ISSN :
1548-3746
Print_ISBN :
978-1-4244-1175-7
Electronic_ISBN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2007.4488600
Filename :
4488600
Link To Document :
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