Title :
Synthesis for advanced ASIC design
Author_Institution :
Cadence Design Syst. Inc., San Jose, CA, USA
Abstract :
This paper describes a new synthesis capability required for the design of advanced ASICs. Called placement-based synthesis (PBS), it specifically addresses the challenges of 0.5 μm design. It allows placement data to be read by logic design tools in order to accurately assess interconnect delays (which account for up to 80% of the overall delay through a path in devices of this size). It then directly and incrementally adjusts the placement in order to correct timing problems and meet performance objectives
Keywords :
application specific integrated circuits; integrated circuit design; logic design; 0.5 micron; ASIC design; interconnect delays; logic design; placement-based synthesis; timing; Application specific integrated circuits; Clocks; Delay estimation; Design methodology; Engines; Foundries; Logic design; Logic devices; Pins; Timing;
Conference_Titel :
WESCON/'93. Conference Record,
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-9970-6
DOI :
10.1109/WESCON.1993.488410
