Title :
Circuit techniques for multi-bit parallel testing of 64 Mb DRAMs and beyond
Author :
Sakuta, T. ; Muranaka, M. ; Matsuura, H. ; Tanaka, H. ; Nakagome, Y. ; Miyazawa, K. ; Ishihara, M.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
Through the use of a high-speed compression circuit that can compress data signals of low amplitude, high-speed 32-b parallel processing tests for 64 MDRAMs have been achieved. Through the use of a low-power dynamic-type differential amplifier, highly compressed 128-b parallel processing tests have been made possible. By including appropriate test circuits based on independent concepts corresponding to the testing of the peripheral circuits and that of the memory cell, the testing function of 64 MDRAMs has become practical. Design features and characteristics of the 64 MDRAM are summarized.<>
Keywords :
DRAM chips; VLSI; integrated circuit testing; 64 Mbit; 64 Mbit DRAM; ULSI; characteristics; circuit techniques; dynamic-type differential amplifier; high-speed compression circuit; multi-bit parallel testing; parallel processing tests; test circuits; testing function; CMOS logic circuits; Circuit testing; Delay; Differential amplifiers; Energy consumption; Laboratories; Parallel processing; Production; Random access memory; Timing;
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
DOI :
10.1109/VLSIC.1992.229240
