Intra-chip address-presetting data-transfer scheme using four-valued encoding

This paper presents a new common-bus architecture for high-speed data transfer, transferring vast quantities of data between modules inside a VLSI chip. In the intra-chip data transfer, the start addresses of the source and destination modules and the number of data are sent to the target modules in the first step, which is called "address presetting". After that, only the data are transferred, using the maximum width of the bus, which results in achieving a high throughput of bus communication. Moreover, the use of multiple-valued data encoding, together with a multiple-valued current-mode circuit technique for multi-level signal detectors, makes it possible to perform higher throughput of data transfer under the bus-width constraint. In the case of a 64-line bus, it is demonstrated that the peak throughput, using the proposed architecture, is 8 times higher than that using a binary bus architecture, based on direct memory access control. Its power dissipation is reduced to about 20 percent in comparison with that of the direct memory access one, under a normalized throughput in a 0.18 μm CMOS process.