A 24GHz multi-phase PLL for optical communication

Speed and noise are always two critical factors to tradeoff in contemporary phase-locked loop (PLL) design. Noise becomes a more serious problem in high frequency system design because the clock period is already comparable to the jitter. Thus, new techniques are imperative to suppress the noise. In this paper, a high-frequency, low-noise PLL is demonstrated as a test vehicle because it is one of the most critical components in wired and wireless communication systems. A multi-phase LC-ring oscillator is designed to effectively achieve both low noise and wide tuning range. A negative impedance amplifier (NIA) charge pump is proposed that can further reduce the noise of the PLL. In addition, a pulse swallow frequency divider is implemented that can program the frequency to the desired value. Finally, comparison of this work to previously published VCOs in phase noise, tuning range and DC power is shown in a table. The simulation demonstrates that the VCO phase noise is -102.19 dBc/Hz at 1 MHz offset.