A single-electron-transistor logic gate family and its application - Part II: design and simulation of a 7-3 parallel counter with linear summation and multiple-valued latch functions

Guidelines for designing multi-input multi-output counters, based on a single-electron transistor (SET) logic gate family, are presented. A counter consisting of an inverting adder, latched multiple-valued (MV) quantizer, and periodic literals can be made extremely compact owing to the high functionality of SETs and a specific design that utilizes limited kinds of transistors and does not require SETs with control gates or devices for level shifting. Circuit simulation, using a physics-based SET model, reveals that the counter operates at a moderately high speed and with ultra-low power consumption.