A neural network embedded processor with a dynamically reconfigurable pipeline architecture

Author

Satonaka, T. ; Tamura, Y. ; Morishita, T. ; Inoue, A. ; Katsu, S. ; Otsuki, T. ; Kano, G.

Author_Institution

Matsushita Electron. Corp., Osaka, Japan

fYear

1992

fDate

4-6 June 1992

Firstpage

18

Lastpage

19

Abstract

A neural network embedded processor with a dynamically reconfigurable pipeline architecture is described. The processor dynamically changes connections between arithmetic units and memories to obtain the optimum pipeline configuration at every step of the network calculation. The processor attains a learning speed of 18 million connection updates per second (MCUPS), which is approximately 20 times that of the conventional digital signal processor. This processor provides expansibility in the calculation through a larger multilayer network by means of a network decomposition and a distributed processing approach.<>

Keywords

neural nets; pipeline processing; reconfigurable architectures; distributed processing approach; dynamically reconfigurable pipeline architecture; expansibility; learning speed; multilayer network; network decomposition; neural network embedded processor; Arithmetic; Circuits; Clocks; Computer architecture; Digital signal processing; Distributed processing; Matrix decomposition; Neural networks; Pipelines; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0701-1

Type

conf

DOI

10.1109/VLSIC.1992.229257

Filename

229257