• DocumentCode
    3267571
  • Title

    Design and verification of parallel multipliers using arithmetic description language: ARITH

  • Author

    Ishida, Kazuya ; Homma, Naofumi ; Aoki, Takafumi ; Higuchi, Tatsuo

  • Author_Institution
    Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
  • fYear
    2004
  • fDate
    19-22 May 2004
  • Firstpage
    334
  • Lastpage
    339
  • Abstract
    This paper proposes the basic concept of an arithmetic description language called ARITH. The use of ARITH makes possible: (i) formal description of arithmetic algorithms, including those using unconventional number systems; (ii) formal verification of the described arithmetic algorithms; and (iii) translation of arithmetic algorithms to equivalent HDL codes. In this paper, we demonstrate the potential of ARITH through an experimental design of parallel multipliers using a binary signed-digit number system.
  • Keywords
    digital arithmetic; formal verification; hardware description languages; logic CAD; multiplying circuits; parallel architectures; ARITH arithmetic description language; algorithm HDL code translation; arithmetic algorithm formal description; binary signed-digit number system; formal verification; parallel multiplier design; unconventional number systems; Arithmetic; Logic design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on
  • ISSN
    0195-623X
  • Print_ISBN
    0-7695-2130-4
  • Type

    conf

  • DOI
    10.1109/ISMVL.2004.1319964
  • Filename
    1319964