Improved write margin for 90nm SOI-7T-SRAM by look-ahead dynamic threshold voltage control

Instability of SRAM memory cells derived from aggressive technology scaling has recently been one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-lV, it unfortunately results in degradation of write margins. Then, we address a new memory cell adopting a look-ahead body-bias which dynamically controls the threshold voltage in order to assist the write operation. Simulation results have shown improvement in both the write margins and access time.