A high-speed parallel pipelined ADC technique in CMOS

Author

Conroy, C.S.G. ; Cline, D.W. ; Gray, P.R.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1992

fDate

4-6 June 1992

Firstpage

96

Lastpage

97

Abstract

A new architecture consisting of a time-interleaved array of pipelined A/D converters (ADCs) is presented. A prototype has been designed consisting of four switched-capacitor (S/C) multistage pipelined ADCs in parallel. Digital error correction is employed to ease comparator accuracy requirements. A key circuit issue is the design of a high-speed sample-and-hold (S/H) amplifier. A fully differential, mostly NMOS, unfolded cascode operational amplifier topology is used. Results from an experimental chip implemented in 1 mu m CMOS are presented.<>

Keywords

CMOS integrated circuits; analogue-digital conversion; parallel architectures; pipeline processing; sample and hold circuits; 11 micron; CMOS; chip architecture; digital error correction; high speed sample and hold amplifier; high-speed parallel pipelined ADC technique; pipelined A/D converters; switched capacitor multistage pipelined ADCs; time-interleaved array; unfolded cascode operational amplifier topology; CMOS technology; Capacitors; Circuits; Computer architecture; MOS devices; Operational amplifiers; Resistors; Samarium; Throughput; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0701-1

Type

conf

DOI

10.1109/VLSIC.1992.229274

Filename

229274