DocumentCode :
3268820
Title :
Advanced microarchitecture simulator for design, verification and synthesis
Author :
Ramachandran, Aswin ; Johnson, Louis G.
Author_Institution :
Oklahoma State Univ., Stillwater
fYear :
2007
fDate :
5-8 Aug. 2007
Firstpage :
875
Lastpage :
878
Abstract :
Accurate functional and timing verification of microarchitecture designs requires detailed models at register-transfer level (RTL). The complexity in microarchitecture designs is foreseeable with the introduction of multi-core processor architectures. Simulations at such a detailed level are computation intensive. A new microarchitecture simulator - OSU AbaKus - is developed to address the simulation speed together with accurate functional and timing design verification. The modular approach of the simulator, that is in close correlation with the digital hardware design enables to add and modify designs easily. A detailed superscalar architecture is tested and the throughput of the simulators is compared with SimpleScalar sim-outorder.
Keywords :
circuit simulation; digital simulation; integrated circuit design; integrated circuit testing; microprocessor chips; OSU AbaKus; advanced microarchitecture simulator; digital hardware design; functional verification; microarchitecture designs; multicore processor architectures; register-transfer level; superscalar architecture testing; timing design verification; Benchmark testing; Computational modeling; Computer architecture; Discrete event simulation; Hardware; Microarchitecture; Multicore processing; Process design; Space exploration; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
Conference_Location :
Montreal, Que.
ISSN :
1548-3746
Print_ISBN :
978-1-4244-1175-7
Electronic_ISBN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2007.4488711
Filename :
4488711
Link To Document :
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