• DocumentCode
    3268958
  • Title

    Formal property verification by abstraction refinement with formal, simulation and hybrid engines

  • Author

    Wang, Dong ; Ho, Pei-Hsin ; Long, Jiang ; Kukula, James ; Zhu, Yunshan ; Ma, Tony ; Damiano, Robert

  • Author_Institution
    Carnegie Mellon Univ., Pittsburgh, PA, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    35
  • Lastpage
    40
  • Abstract
    We present RFN, a formal property verification tool based on abstraction refinement. Abstraction refinement is a strategy for property verification. It iteratively refines an abstract model to better approximate the behavior of the original design in the hope that the abstract model alone will provide enough evidence to prove or disprove the property. However, previous work on abstraction refinement was only demonstrated on designs with up to 500 registers. We developed RFN to verify real-world designs that may contain thousands of registers. RFN differs from the previous work in several ways. First, instead of relying on a single engine, RFN employs multiple formal verification engines, including a BDD-ATPG hybrid engine and a conventional BDD-based fixpoint engine, for finding error traces or proving properties on the abstract model. Second, RFN uses a novel two-phase process involving 3-valued simulation and sequential ATPG to determine how to refine the abstract model. Third, RFN avoids the weakness of other abstraction-refinement algorithms-finding error traces on the original design, by utilizing the error trace of the abstract model to guide sequential ATPG to find an error trace on the original design. We implemented and applied a prototype of RFN to verify various properties of real-world RTL designs containing approximately 5,000 registers, which represents an order of magnitude improvement over previous results. On these designs, we successfully proved a few properties and discovered a design violation.
  • Keywords
    automatic test pattern generation; binary decision diagrams; fixed point arithmetic; formal verification; logic testing; sequential circuits; BDD-ATPG hybrid engine; BDD-based fixpoint engine; RFN; abstraction refinement; design violation; formal property verification; multiple formal verification engines; real-world designs; sequential ATPG; two-phase process; Algorithm design and analysis; Automatic test pattern generation; Boolean functions; Data structures; Engines; Formal verification; Manufacturing; Permission; Prototypes; Safety;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2001. Proceedings
  • ISSN
    0738-100X
  • Print_ISBN
    1-58113-297-2
  • Type

    conf

  • DOI
    10.1109/DAC.2001.156104
  • Filename
    935473