Title :
A 200 Mb/s analog DFE read channel
Author :
Sands, N.P. ; Hauser, M.W. ; Liang, Guozheng ; Groenewold, G. ; Lam, Stanley ; Chao-Ho Lin ; Kuklewicz, J. ; Lang, L. ; Dakshinamurthy, R.
Author_Institution :
Philips Semicond., Sunnyvale, CA, USA
Abstract :
A 200 Mb/s read-channel IC realizes an enhanced decision-feedback equalizer (DFE) with a combination of continuous and discrete time analog and digital signal processing. The design uses a 20 GHz peak-f/sub T/, BiCMOS process operating at 5 V, with a power consumption of approximately 700 mW. All associated functions are included: bit detection, RLL encoder/decoder, servo demodulation, and write precompensation. Data rate range is 64200 Mb/s at a normalized recording density of 1.8-2.4.
Keywords :
BiCMOS analogue integrated circuits; analogue processing circuits; compensation; decision feedback equalisers; demodulation; hard discs; runlength codes; 200 Mbit/s; 5 V; 700 mW; BiCMOS process; RLL encoder/decoder; analog DFE read channel IC; bit detection; continuous signal processing; decision-feedback equalizer; discrete time signal processing; normalized recording density; power consumption; servo demodulation; write precompensation; Analog integrated circuits; BiCMOS integrated circuits; Decision feedback equalizers; Decoding; Demodulation; Digital integrated circuits; Digital signal processing; Energy consumption; Process design; Servomechanisms;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488519
