Title :
RACER: a reconfigurable constraint-length 14 Viterbi decoder
Author :
Yeh, David ; Feygin, Gennady ; Chow, Paul
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
This paper describes the architecture and implementation of a constraint-length 14 Viterbi decoder that achieves a decoding rate of 41 Kbits/s. The system uses 36 Xilinx XC4010 FPGAs with seven processor cards and a custom backplane to implement a multi-ring general cascade Viterbi decoder architecture. The paper also shows how to achieve decoding rates of 1 Mbit/s using current FPGA technology. Comparisons are made to JPL´s big Viterbi decoder, which uses custom ASICs
Keywords :
Viterbi decoding; field programmable gate arrays; reconfigurable architectures; RACER; Xilinx XC4010 FPGAs; custom backplane; reconfigurable constraint-length 14 Viterbi decoder; Viterbi decoding;
Conference_Titel :
FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-7548-9
DOI :
10.1109/FPGA.1996.564746
