Low-power and low-complexity architecture for H.264/AVC video decoder

This work proposes an architecture for the H.264/AVC video decoder, of which each functional unit is modularly pipelined and optimized to reduce its hardware complexity. The local buffers are adequately allocated to expedite data communication and to minimize the data access from external memory, thereby to raise computation efficiency and to lower power consumption. By using the cell library of the TSMC 0.25 mum CMOS technology, the proposed hardware core of the H.264/AVC video decoder with a die size of 12.86 mum² consumes 217.2 mW at 2.5 V and 27 MHz to yield a decoding throughput rate of 30 CIF frames per second. As compared to the conventional H.264/AVC video decoder, the proposed video decoder takes less power and hardware cost.