Title :
A 622 Mb/s CMOS clock recovery PLL with time-interleaved phase detector array
Author :
Inyeol Lee ; Changsik Yoo ; Wonchan Kim ; Sanghoon Chai ; Wonchul Song
Author_Institution :
Seoul Nat. Univ., South Korea
Abstract :
A 622 Mb/s clock recovery PLL for SDH/SONET OC-12 is implemented in a 0.8 /spl mu/m CMOS technology. With time-interleaved phase detection scheme, this PLL performs clock recovery and 1:8 demultiplexing simultaneously. It dissipates 200 mW with a single 5 V supply, whose core occupies 800/spl times/900 /spl mu/m/sup 2/. RMS jitter of the recovered 78 MHz clock is 46 ps (0.36%).
Keywords :
CMOS digital integrated circuits; SONET; clocks; demultiplexing equipment; digital phase locked loops; jitter; synchronous digital hierarchy; 0.8 micron; 200 mW; 46 ps; 5 V; 622 Mbit/s; 78 MHz; CMOS; RMS jitter; SDH/SONET OC-12; clock recovery PLL; demultiplexing; time-interleaved phase detector array; Charge pumps; Clocks; Detectors; Jitter; Phase detection; Phase locked loops; Phased arrays; Sampling methods; Sensor arrays; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488569
