• DocumentCode
    3270137
  • Title

    A 0.5V high speed DRAM charge transfer sense amplifier

  • Author

    Chow, Hwang-Cherng ; Hsieh, Chaung-Lin

  • Author_Institution
    Chang Gung Univ., Taoyuan
  • fYear
    2007
  • fDate
    5-8 Aug. 2007
  • Firstpage
    1293
  • Lastpage
    1296
  • Abstract
    A new charge transfer sense amplifier scheme is proposed for high speed 0.5 V DRAMs. The combination of both cross-coupled structure and boost capacitance of the proposed sense amplifier leads to the maximum voltage difference between sense nodes and 40% faster operation than prior art circuits.
  • Keywords
    DRAM chips; amplifiers; boost capacitance; cross-coupled structure; high speed DRAM charge transfer sense amplifier; voltage 0.5 V; Art; CMOS technology; Capacitance-voltage characteristics; Charge transfer; Circuit simulation; Low voltage; Parasitic capacitance; Random access memory; Signal restoration; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
  • Conference_Location
    Montreal, Que.
  • ISSN
    1548-3746
  • Print_ISBN
    978-1-4244-1175-7
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2007.4488787
  • Filename
    4488787
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3270137