Circuit techniques for 10 and 20 Gb/s clock recovery using a fully balanced narrowband regenerative frequency divider with 0.3 /spl mu/m HEMTs [SDH/SONET]

Author

Zhi-Gong Wang ; Berroth, M. ; Thiede, A. ; Rieger-Motzer, M. ; Hofmann, P. ; Hulsmann, A. ; Kohler, K. ; Raynor, B. ; Schneider, J. ; Briggmann, D.

Author_Institution

Fraunhofer-Inst. for Appl. Solid-State Phys., Freiburg, Germany

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

204

Lastpage

205

Abstract

The circuit consists of four subcircuits: the preprocessor, the narrowband regenerative frequency divider (NRFD), the phase-shifting amplifier, and the limiting amplifier. The CR circuit is fully-balanced and can be operated in two modes. At 10 Gb/s input data, the tank circuit of the preprocessor resonates at the second harmonic of the clock frequency. This mode can be used for 10 Gb/s direct data decision. At 20 Gb/s the tank circuit resonates at the fundamental frequency of the clock signal. This mode is optimal for a 20 Gb/s parallel data decision.

Keywords

HEMT integrated circuits; SONET; clocks; frequency dividers; synchronous digital hierarchy; 0.3 micron; 10 Gbit/s; 20 Gbit/s; HEMTs; SDH/SONET; clock recovery; direct data decision; fully balanced narrowband regenerative frequency divider; limiting amplifier; parallel data decision; phase-shifting amplifier; second harmonic; tank circuit; Chromium; Clocks; Filters; Frequency conversion; HEMTs; Inductors; MODFETs; Monolithic integrated circuits; Narrowband; Phase locked loops;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488572

Filename

488572