Title :
A 56-entry instruction reorder buffer
Author :
Gaddis, N.B. ; Butler, J.R. ; Kumar, A. ; Queen, W.J.
Author_Institution :
Hewlett-Packard Co., Fort Collins, CO, USA
Abstract :
A speculative execution high-end PA-RISC CPU has two 28-entry out-of-order instruction reorder buffers (IRBs), one for alu/floating point operations and one for memory operations. The IRBs are capable of inserting any combination of four instructions per cycle. Each cycle, the IRBs launch up to four instructions for execution, two from the ALU IRB and two from the MEM IRB. Up to four instructions (two from each IRB) retire each cycle. The insert, launch and retire mechanisms of this out-of-order machine contain 850 k transistors in 52.6 mm/sup 2/.
Keywords :
buffer circuits; instruction sets; microprocessor chips; parallel architectures; reduced instruction set computing; ALU/floating point operations; high-end PA-RISC CPU; memory operations; multi-entry instruction reorder buffer; out-of-order execution; Broadcasting; Circuits; Delay; Frequency; Out of order; Performance gain; Permission; Wires; Writing;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488575
