Title :
A 160 MHz 32 b 0.5 W CMOS RISC microprocessor
Author :
Montanaro, J. ; Witek, R.T. ; Anne, K. ; Black, A.J. ; Cooper, E.M. ; Dobberpuhl, D.W. ; Donahue, P.M. ; Eno, J. ; Farell, A. ; Hoeppner, G.W. ; Kruckemyer, D. ; Lee, T.H. ; Lin, P. ; Madden, L. ; Murray, D. ; Pearce, M. ; Santhanam, S. ; Snyder, K.J. ; S
Author_Institution :
Digital Equipment Corp., Austin, TX, USA
Abstract :
This custom VLSI implementation of a microprocessor architecture delivers 184 Drystone/MIPS at 162 MHz dissipating 0.5 W using an 1.5 V internal supply. The chip may also be operated at 215 MHz with a 2.0 V internal supply dissipating 1.1 W. The external interface always runs at 3.3 V. The die contains 2.1 M transistors and measures 7.8/spl times/6.4 mm/sup 2/. It is fabricated in 2.0 V 0.35 /spl mu/m 3-layer metal CMOS and packaged in a 144-pin thin quad flat pack. Clock generation uses an on-chip PLL with 3.68 MHz input clock to minimize high frequency clock signals on the board. The chip is pseudo-static and the internal clocks may be stopped in either phase to minimize power consumption.
Keywords :
CMOS digital integrated circuits; VLSI; application specific integrated circuits; microprocessor chips; reduced instruction set computing; 0.35 micron; 0.5 W; 1.5 V; 160 MHz; 32 bit; CMOS RISC microprocessor; custom VLSI; internal clock; on-chip PLL; power dissipation; pseudo-static chip; quad flat pack; three-layer metal process; Clocks; Electronics packaging; Energy consumption; Frequency; Microprocessors; Phase locked loops; Reduced instruction set computing; Semiconductor device measurement; Signal generators; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488576
