Title :
A 200 MHz 2.5 V 4 W superscalar RISC microprocessor
Author :
Sanchez, Hector Eloys ; Eisen, L. ; Croxton, C. ; Piejko, A. ; Nicoletta, C. ; Vo, Ivan ; Branson, B. ; Wen Wang ; Quan Nguyen ; Buti, T. ; Hsu, L. ; Saccamango, M.J. ; Ratanaphanyara, S. ; Philip, Riya ; Alvarez, J. ; Weitzel, S. ; Gerosa, G.
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
This RISC microprocessor is based on a microarchitecture designed in a 2.5 V CMOS technology. The 78.75 mm/sup 2/ design features dual 16 kB instruction and data caches, a floating-point unit, an integer unit, a branch unit, a load/store unit, and a system unit. Two instructions per cycle can be dispatched in this superscalar design. The user-configurable multiplying PLL provides a processor clock at 2/spl times/, 2.5/spl times/, 3/spl times/, 3.5/spl times/, 4/spl times/, 4.5/spl times/, 5/spl times/, 5.5/spl times/, and 6/spl times/ the bus clock frequency. Testability features include level-sensitive-scan-design (LSSD), array-built-in-self-test (ABIST) logic for cache and tag arrays, and a JTAG interface.
Keywords :
CMOS digital integrated circuits; microprocessor chips; reduced instruction set computing; 2.5 V; 200 MHz; 4 W; CMOS technology; JTAG interface; array-built-in-self-test logic; branch unit; cache array; data cache; floating-point unit; instruction cache; integer unit; level-sensitive-scan-design; load/store unit; microarchitecture; processor clock; superscalar RISC microprocessor; system unit; tag array; testability; user-configurable multiplying PLL; CMOS technology; Capacitance; Clocks; Energy consumption; Energy management; Logic arrays; Logic testing; Microprocessors; Phase locked loops; Reduced instruction set computing;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488578
