Title :
Two-stage phase/frequency detecting CPPLL
Author :
Wei, Jianjun ; Jia, Xinzhang
Author_Institution :
Sch. of Comput., Northwest Polytech. Univ., Xi´´an
Abstract :
CPPLL(charge pump phase-locked loops), the input-output characteristic of PFD(phase/frequency detector) is studied. It shows that the outputs of PFD not only express the phase and frequency differences of inputs, but also vary slowly. Based on the study, the two-stage phase/frequency detecting is proposed and the CPPLL with this function is realized. The outputs of the one-stage PFD are delayed and then detected by the two-stage PFD. The outputs of the two-stage PFD activate a charge pump with large current to tune the control voltage of VCO(voltage control oscillator) coarsely. Meantime, the outputs of the one-stage PFD activate the other charge pump with small current to tune the control voltage finely. The results show that this structure reduces the locking time by 7.46%-8.76%.
Keywords :
charge pump circuits; circuit tuning; phase detectors; phase locked loops; voltage-controlled oscillators; CPPLL; VCO; charge pump phase-locked loops; control voltage tuning; frequency detector; input-output characteristic; two-stage phase detector; voltage control oscillator; Charge pumps; Circuits; Delay; Microelectronics; Phase detection; Phase frequency detector; Phase locked loops; Telecommunication control; Voltage control; Voltage-controlled oscillators; phase/frequency detecting; ripple; tune coarsely;
Conference_Titel :
Telecommunication Networks and Applications Conference, 2007. ATNAC 2007. Australasian
Conference_Location :
Christchurch
Print_ISBN :
978-1-4244-1557-1
Electronic_ISBN :
978-1-4244-1558-8
DOI :
10.1109/ATNAC.2007.4665262
