One-transistor-cell multiple-valued CAM for a collision detection VLSI processor

Author

Hanyu, T. ; Kanagawa, N. ; Kameyama, M.

Author_Institution

Dept. of Comput. & Math. Sci., Tohoku Univ., Sendai, Japan

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

264

Lastpage

265

Abstract

Parallel search and parallel comparison are major advantages of content-addressable memories (CAMs) over random-access memories. However, a CAM is more complex and has lower storage density than a conventional address-based memory because of the overhead involved in the storage, comparison, manipulation, and output-selection logic. A CAM based on multiple-valued logic is proposed for high-speed word-parallel magnitude comparison. A typical application of the multiple-valued CAM is a collision detection VLSI processor for intelligent vehicles.

Keywords

VLSI; content-addressable storage; digital signal processing chips; integrated memory circuits; multivalued logic circuits; path planning; collision detection VLSI processor; content-addressable memory; high-speed word-parallel magnitude comparison; multiple-valued logic; one-transistor-cell CAM; parallel comparison; parallel search; storage density; CADCAM; Computer aided manufacturing; Concurrent computing; Logic arrays; MOSFETs; Nonvolatile memory; Threshold voltage; Timing; Vehicle detection; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488616

Filename

488616