A 32-bank 1 Gb DRAM with 1 GB/s bandwidth

Author

Jei-Hwan Yoo ; Chang Hyun Kim ; Kyu Chan Lee ; Kye-Hyun Kyung ; Seung-Moon Yoo ; Jung Hwa Lee ; Moon-Hae Son ; Jin-Man Han ; Bok-Moon Kang ; Ejaz Haq ; Sang-Bo Lee ; Jai-Hoon Sim ; Joung-Ho Kim ; Byung-Sik Moon ; Keum-Yong Kim ; Jae Gwan Park ; Kyu-Phil L

Author_Institution

Samsung Electron. Co. Ltd., Kyungki-Do, South Korea

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

378

Lastpage

379

Abstract

This 32-bank 1 Gb DRAM features: (1) a merged bank architecture (MBA) that results in only 3% die area penalty for 32-bank operation; (2) a source-synchronous I/O interface (SSI) that achieves 1 GB/s bandwidth with low power consumption; (3) flexible block redundancy that allows freedom of repair to anywhere within each half-Gb array; and (4) extended small swing read and single-I/O line driving write which result in 30% power reduction. The DRAM chip is implemented in a 0.16 /spl mu/m twin-well CMOS process.

Keywords

CMOS memory circuits; DRAM chips; fault tolerant computing; memory architecture; redundancy; 0.16 micron; 1 GB/s; 1 Gbit; 32-bank operation; DRAM chip; dynamic RAM; flexible block redundancy; low power consumption; merged bank architecture; source-synchronous I/O interface; twin-well CMOS process; Bandwidth; CMOS process; CMOS technology; Capacitance; Circuit testing; Delay; Fabrication; Packaging; Random access memory; Solid state circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488725

Filename

488725