A Theoretical Research on Program Instruction Level Parallelism to Guide Microprocessor Design

As the number of transistors integrated in a microprocessor chip increases continuously, more and more researches focus on how to efficiently utilize the on-chip resources recently. Research on the relationship between the instruction window size and program ILP can guide the design of clustered architecture and heterogeneous CMP. A theoretical model is proposed for the instruction window of superscalar processors in this paper. Using this model, an optimized algorithm can be applied to calculate the ideal IPC based on the dynamic instruction dependency statistics of benchmarks. It can be used to explain the square root law presented by the IW characteristic. And the relationship between the ideal IPC and instruction window size can be more accurately modeled as the harmonic curve. Compared with the traditional simulation method, this analytical model can analyze the interaction between the program characteristic, instruction window size and program ILP theoretically and help to explore the workload design space. This model can also be combined with the statistical simulation method to evaluate the microprocessor performance rapidly. The instruction window model will be integrated into the performance analysis platform of the Godson-2 processor to aid the performance analysis work.