Low Power Techniques on a High Speed Floating-point Adder Design

A 64 bit low power, high speed floating-point adder design is presented in this paper. The proposed floating-point adder is based on dual path architecture, and both dynamic and leakage power are reduced by exploiting architecture opportunities to minimize switching activity and maximize the stack effect of the circuits concurrently. Experimental result based on 130 nm CMOS standard cell design shows that average power consumptions of the FP adder can be reduced by 61.4% with proposed low power techniques.