A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSls

Author

Miyazaki, Masayuki ; Mizuno, Hiroyuki ; Ishibashi, Koji

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

1998

fDate

10-12 Aug. 1998

Firstpage

48

Lastpage

53

Abstract

In a speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) circuit, the substrate bias is controlled so that delay in the circuit stays constant. Distributions of device speeds are squeezed under fast-operation conditions. With a ring oscillator using 0.25 /spl mu/m CMOS devices as a test circuit, we found that the worst-case operating frequency was improved from 20 MHz to 55 MHz, and the fluctuation of the operating frequency was suppressed from 44% to 15% while the supply-voltage variation was under 0.1 V with a 1.8 V supply voltage.

Keywords

CMOS digital integrated circuits; compensation; delays; fluctuations; high-speed integrated circuits; large scale integration; low-power electronics; timing; 0.25 micron; 1.8 V; 55 MHz; constant delay; delay distribution squeezing scheme; fast-operation conditions; low voltage LSls; operating frequency fluctuation suppression; speed-adaptive threshold-voltage CMOS; substrate bias control; supply-voltage variation reduction;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium on

Conference_Location

Monterey, CA, USA

Print_ISBN

1-58113-059-7

Type

conf

Filename

708154