Memory modeling for system synthesis

We present our methodology for developing models of on-chip SRAM memory organizations. The models were created to enable the quick evaluation of energy, area, and performance of different memory configurations considered during synthesis. The models are defined in terms of parameters, such as size and mode of operation, which are known at synthesis time. Our methodology does not require knowledge of the underlying memory circuitry and provides models with average percentage errors within 8%. We found that only 10 different memories from a large span of possible memory sizes are needed to obtain reasonably accurate models, with average errors within 15%. We further use these models to evaluate different low power memory organizations and have seen energy reductions of up to 88%. In this paper we present our modeling methodology, discuss the important aspects in developing the models, and show results of using the models in evaluating low power memory organizations.