• DocumentCode
    327248
  • Title

    Voltage scheduling problem for dynamically variable voltage processors

  • Author

    Ishihara, Tohru ; Yasuura, Hiroto

  • Author_Institution
    Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
  • fYear
    1998
  • fDate
    10-12 Aug. 1998
  • Firstpage
    197
  • Lastpage
    202
  • Abstract
    This paper presents a model of dynamically variable voltage processors and basic theorems for power-delay optimization. A static voltage scheduling problem is also proposed and formulated as an integer linear programming (ILP) problem. In the problem, we assume that a core processor can vary its supply voltage dynamically, but can use only a single voltage level at a time. For a given application program and a dynamically variable voltage processor, a voltage scheduling which minimizes energy consumption under an execution time constraint can be found.
  • Keywords
    CMOS digital integrated circuits; VLSI; circuit optimisation; integer programming; integrated circuit design; linear programming; low-power electronics; scheduling; core processor; digital CMOS; dynamically variable voltage processors; energy consumption; execution time constraint; integer linear programming; power-delay optimization; static voltage scheduling problem; voltage level; voltage scheduling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium on
  • Conference_Location
    Monterey, CA, USA
  • Print_ISBN
    1-58113-059-7
  • Type

    conf

  • Filename
    708188