Microprocessor clock distribution

Summary form only given. A microprocessor´s clock distribution network provides a spine around which the performance is built. Clock skew penalizes the overall performance by adding to the maximum delay path. In addition it subtracts from minimum delay paths increasing the risk of a hold time failure. Uncompensated delay in the clock distribution shifts I/O timings, increasing output delays and hold times. Variation in the delay causes jitter, increasing setup/hold and minimum/maximum delay windows. Determining the expected skew and jitter of a clock distribution network is thus essential to projecting the performance of a microprocessor and its I/O capability. In addition, overestimating the skew will lead to over designing the minimum delay paths of the processor wasting area and power, while underestimating the skew will lead to hold time violations and functional failures under some operating conditions. All of these factors must be considered in order to accurately model and minimize the skew and jitter ofthe clock distribution network of a microprocessor