DocumentCode :
3273473
Title :
A simplified router architecture for the modified Fat Tree Network-on-Chip topology
Author :
Bouhraoua, A. ; Diraneyya, O. ; Elrabaa, M.E.
Author_Institution :
King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
fYear :
2009
fDate :
16-17 Nov. 2009
Firstpage :
1
Lastpage :
4
Abstract :
The architecture of the class of routers to implement the modified Fat Tree topology is shown. The router architecture is buffer-less with a simplified routing function. The routing function is obtained from a model that describes the Fat Tree topology and from where the equations governing the routing circuitry are derived. A parameterized router model is developed and coded in verilog. A modified Fat Tree network generator that uses the router model is also developed. The generator produces verilog files directly used in functional simulation.
Keywords :
hardware description languages; network-on-chip; telecommunication network routing; telecommunication network topology; fat tree topology; network-on-chip; router architecture; routing function; verilog; Circuit topology; DH-HEMTs; Integrated circuit interconnections; Minerals; Multiprocessor interconnection networks; Network topology; Network-on-a-chip; Petroleum; Routing; Throughput; ASICs; Fat Tree; Interconnection Networks; Networks-On-Chip; Routing; Systems-on-Chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
NORCHIP, 2009
Conference_Location :
Trondheim
Print_ISBN :
978-1-4244-4310-9
Electronic_ISBN :
978-1-4244-4311-6
Type :
conf
DOI :
10.1109/NORCHP.2009.5397806
Filename :
5397806
Link To Document :
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