Impact of intra-die random variations on clock tree

Random intra-die variation is an ever-increasing concern in the microelectronics industry. Analysis solutions available today are complex to implement industrially. Most works on intra-die variations concentrate on systematic mismatch that is ameliorated through manufacturing improvements (e.g. regularity improvement in Design Rule Manual). Statistical static timing analysis (SSTA) is said to be a good estimator of random intra-die variations but lacks ease of deployment and requires lots of effort in characterizing the libraries. Even then, extensive analysis tools do not necessarily provide insights about the differences between the impact on various cells and their context. In this work, we have tried to find a rapidly implementable solution in commercial Computer Aided Design (CAD) tools using industrial models to reduce the impact of random intra-die variations at cell level and to find the basic set of parameters on which to base the usability of standard cells. We have characterized the impact of random variations on some basic cells used in clock like structures to achieve the said purpose.