Title :
A 2–5 Gb/s fully differential 3X oversampling CDR for high-speed serial data link
Author :
Kiddinapillai, Nathan ; Kwasniewski, Tad
Author_Institution :
Carleton Univ., Ottawa, ON, Canada
Abstract :
This paper presents the design and implementation of a fully differential 3X oversampling clock and data recovery (CDR) circuit for high-speed serial data link. The CDR is capable of operating at any speed from 2 to 5 Gb/s. The architecture of the CDR replaces the analog VCO and loop filter used in analog PLL based CDR with digital circuits. The CDR uses a digital threshold decision technique to improve the jitter tolerance performance. System level simulation shows that the CDR has a high frequency jitter tolerance of 0.67 UI and acquisition time of 8 baud period. The CDR is implemented in 65 nm CMOS process technology. The post-layout simulation is performed for 27-1 PRBS data. The CDR consumes 39 mW from 1.1 V power supply at 5 Gb/s. The core CDR circuit occupies an area of 0.013 mm2.
Keywords :
CMOS integrated circuits; analogue integrated circuits; circuit simulation; clock and data recovery circuits; integrated circuit design; phase locked loops; CDR circuit; analog PLL; analog VCO; bit rate 2 Gbit/s to 5 Gbit/s; clock and data recovery; fully differential oversampling; high frequency jitter tolerance; high-speed serial data link; loop filter; power 39 mW; power supply; voltage 1.1 V; CMOS process; CMOS technology; Circuit simulation; Clocks; Digital circuits; Digital filters; Frequency; Jitter; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
NORCHIP, 2009
Conference_Location :
Trondheim
Print_ISBN :
978-1-4244-4310-9
Electronic_ISBN :
978-1-4244-4311-6
DOI :
10.1109/NORCHP.2009.5397815