Reduction of Reset Current in NiO-ReRAM Brought about by Ideal Current Limiter

Author

Kinoshita, K. ; Tsunoda, K. ; Sato, Y. ; Noshiro, H. ; Yamazaki, Y. ; Fukano, T. ; Yagaki, S. ; Aoki, M. ; Sugiyama, Y.

Author_Institution

Fujitsu Lab. LTD., Atsugi

fYear

2007

fDate

26-30 Aug. 2007

Firstpage

66

Lastpage

67

Abstract

In this paper, we fabricated 1T1R NiO-ReRAM test circuits based on 0.18 mum CMOS technology and observed notable suppression of I_reset by imposing current compliance I_comp using a cell transistor. Reducing the stray capacitance between Pt/NiO/Pt and the cell transistor used as a current limiter is crucial in this issue. This enabled the systematic measurement of I_comp dependence of l_reset for I_comp < 1 mA and I_reset ap I_comp was observed for 150 muA les I_comp les950 muA.

Keywords

CMOS integrated circuits; current limiters; nickel compounds; platinum; random-access storage; CMOS technology; NiO; NiO-ReRAM test circuits; Pt; cell transistor; current compliance; current limiter; reset current; size 0.18 mum; stray capacitance; CMOS technology; Capacitance; Circuit testing; Current limiters; Flash memory; Joining processes; Monitoring; Read-write memory; Sputtering; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE

Conference_Location

Monterey, CA

Print_ISBN

1-4244-0753-2

Electronic_ISBN

1-4244-0753-2

Type

conf

DOI

10.1109/NVSMW.2007.4290583

Filename

4290583