SystemC Transaction Level Modeling and Verification of IEEE 802.15.3 MAC

As implementation technology has evolved into increasingly complex integrated circuits and time-to-market pressure increases day by day, system level design issues become more critical in the context of system on Chip, which gives rise to the need for abstract executable specifications (models) covering both hardware and embedded software. The new capabilities of SystemC 2.0, such as those added for transaction-based communication and test-bench specification and monitoring, facilitate this SoC modeling. In this paper, we present a transaction level modeling and verification method of IEEE 802.15.3 MAC chip based on SystemC 2.0, which include an accuracy video model and a transaction level system model of IEEE 802.15.3 MAC protocol. With the proposed scheme, we can get a reusable test bench which can be used at both transaction level and register transfer level. In this case, the verification efficiency and accuracy will be greatly improved. Specially, the transaction level model can significantly reduce product development risk while avoiding expensive over- engineering by ensuring the architecture meets all performance, power and cost requirements prior to implementation, allowing design resources to focus on value- added functions.