Title :
Self-timed circuits using DCVSL semi-bundled delay wrappers
Author :
Yang, Jung-Lin ; Brunvand, Erik
Author_Institution :
Inst. of Electron. Eng., Southern Taiwan Univ. of Technol., Tainan, Taiwan
Abstract :
We present a technique for generating robust self-timed completion signals for general dynamic datapath circuits. The wrapper circuit is based on our previous domino semi-bundled delay (SBD) circuits, but uses DCVSL circuits in the wrapper for higher performance. We describe the basic SBD-DCVSL building blocks in the template with respect to their circuit structures and operational behavior. These DCVSL SBD circuits show better performance, exhibit reduced overhead, and require reduced operating margins for the matched delay compared with the domino version. The DCVSL wrapper can also identify a class of delay faults in the data path.
Keywords :
delay circuits; DCVSL semibundled delay wrappers; domino semibundled delay circuits; self-timed circuits; Circuit synthesis; Control system synthesis; Control systems; Data engineering; Delay effects; Hazards; Robustness; Signal generators; Signal synthesis; Wires;
Conference_Titel :
Intelligent Signal Processing and Communication Systems, 2005. ISPACS 2005. Proceedings of 2005 International Symposium on
Print_ISBN :
0-7803-9266-3
DOI :
10.1109/ISPACS.2005.1595441