A study of 3D Network-on-Chip design for data parallel H.264 coding

In this paper, we study and analyze different Network-on-Chip (NoC) designs for MPEG-4/H.264 coding. The encoding and decoding processes of H.264 have been analyzed. We discuss the parallelism of H.264, and an open-source encoding program is used as a case study. The contribution of this paper lies in the NoC design method and performance evaluation of data parallel H.264 coder. It is shown in our study that the inter-thread data dependency of shared reads and writes are performance bottlenecks. Different non-uniform cache access NoC designs have been explored. Two-dimensional (2D) and three-dimensional (3D) NoCs have been analyzed in terms of hop count and heat dissipation. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in two 3D NoC designs are reduced up to 34% compared with the 2D NoC. It is also shown that the heat dissipation is a trade-off consideration in improving the performance of 3D IC. Our analysis and experiment results provide a guideline to design efficient 3D NoCs for data parallel H.264 coding applications.